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MPC7457RXNXPNS/D Rev. 0, 2/2003 MPC7457 Part Number Specification for the MPC74x7RXnnnnNx Series
Motorola Part Numbers Affected: XPC7457RX1000NB XPC7447RX1000NB
This document describes part-number-specific changes to recommended operating conditions and revised electrical specifications, as applicable, from those described in the general MPC7457 RISC Microprocessor Hardware Specifications (Order No. MPC7457EC/D). Specifications provided in this document supersede those in the MPC7457 RISC Microprocessor Hardware Specifications, Rev. 0 or later, for the part numbers listed in Table A only. Specifications not addressed herein are unchanged. Because this document is frequently updated, refer to http://www.motorola.com/semiconductors or to your Motorola sales office for the latest version. Note that headings and table numbers in this document are not consecutively numbered. They are intended to correspond to the heading or table affected in the general hardware specification. Part numbers addressed in this document are listed in Table A.
Table A. Part Numbers Addressed by this Data Sheet
Operating Conditions Motorola Part Number CPU Frequency (MHz) 1000 Tj (C) Significant Differences from Hardware Specification
VDD
XPC7457RX1000NB XPC7447RX1000NB
1.1 V 50 mV 0 to 105 Modified core frequency and voltage to reduce power consumption, modified processor bus clock frequency and AC timing.
Note: The X prefix in a Motorola part number designates a "Pilot Production Prototype" as defined by Motorola SOP 3-13. These are from a limited production volume of prototypes manufactured, tested, and Q.A. inspected on a qualified technology to simulate normal production. These parts have only preliminary reliability and characterization data. Before pilot production prototypes may be shipped, written authorization from the customer must be on file in the applicable sales office acknowledging the qualification status and the fact that product changes may still occur while shipping pilot production prototypes.
PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE
Features
1.1
*
Features
Power management -- 1.1-V processor core
This section summarizes changes to the features of the MPC7457 described in the MPC7457 RISC Microprocessor Hardware Specifications.
1.3 General Parameters
* Core power supply: 1.1 V 50 mV DC nominal
1.5.1 DC Electrical Characteristics
Table 4 provides the recommended operating conditions for the MPC7457 part numbers described herein.
Table 4. Recommended Operating Conditions
Characteristic Core supply voltage PLL supply voltage Symbol VDD AVDD Recommended Value 1.1 V 50 mV 1.1 V 50 mV Unit V V
Note: These are the recommended and tested operating conditions. Proper device operation outside of these conditions is not guaranteed.
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MPC7457 Part Number Specification for the MPC74x7RXnnnnNx Series PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE
MOTOROLA
General Parameters
Table 7 provides the power consumption for the MPC7457 part numbers described herein.
Table 7. Power Consumption for MPC7457
Processor (CPU) Frequency Unit 1000 MHz Full-Power Mode Typical Maximum Doze Mode Typical Nap Mode Typical Sleep Mode Typical TBD Deep Sleep Mode (PLL Disabled) Typical 2.0 W 1, 3 W 1, 2 TBD W 1, 2 -- W 4 7.5 12.5 W W 1, 3 1, 2 Notes
Notes: 1. These values apply for all valid processor bus and L3 bus ratios. The values do not include I/O supply power (OVDD and GVDD) or PLL supply power (AVDD). OVDD and GVDD power is system dependent, but is typically <5% of VDD power. Worst case power consumption for AVDD < 3 mW. 2. Maximum power is the maximum measured at nominal VDD and maximum operating junction temperature (see Table 4) while running an entirely cache-resident, contrived sequence of instructions which keep all the execution units maximally busy. 3. Typical power is an average value measured at the nominal recommended VDD (see Table 4) and 65C while running the Dhrystone 2.1 benchmark and achieving 2.3 Dhrystone MIPs/MHz. 4. Doze mode is not a user-definable state; it is an intermediate state between Full-Power and either Nap or Sleep mode. As a result, power consumption for this mode is not tested.
MOTOROLA
MPC7457 Part Number Specification for the MPC74x7RXnnnnNx Series PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE
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General Parameters
Table 8 provides the clock AC timing specifications for the MPC7457 part numbers described herein.
Table 8. Clock AC Timing Specifications
At recommended operating conditions. See Table 4.
Maximum Processor Core Frequency Characteristic Symbol Min Processor frequency VCO frequency SYSCLK frequency SYSCLK cycle time fcore fVCO fSYSCLK tSYSCLK 500 1000 33 7.5 1000 MHz Max 1000 2000 133 30 MHz MHz MHz ns 1 1 Unit Notes
Note: 1. Caution: The SYSCLK frequency, PLL_CFG[0:4] settings must be chosen such that the resulting SYSCLK (bus) frequency, CPU (core) frequency, and PLL (VCO) frequency do not exceed their respective maximum or minimum operating frequencies (see Table 4 in the MPC7457 RISC Microprocessor Hardware Specifications). Refer to the PLL_CFG[0:4] signal description in Section 1.9.1, "PLL Configuration," for valid PLL_CFG[0:4] settings.
1.5.2.2
Processor Bus AC Specifications
Table 9 provides the processor bus AC timing specifications for the MPC7457 as defined in Figure 4 and Figure 5. Timing specifications for the L3 bus are provided in Section 1.5.2.3, "L3 Clock AC Specifications."
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MPC7457 Part Number Specification for the MPC74x7RXnnnnNx Series PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE
MOTOROLA
General Parameters Table 1-9. Processor Bus AC Timing Specifications 1
At recommended operating conditions. See Table 4.
All Speed Grades Parameter Symbol 2 Min Mode select input setup to HRESET HRESET to mode select input hold Input setup times: A[0:35], AP[0:4] D[0:63], DP[0:7] AACK, ARTRY, BG, CKSTP_IN, DBG, DTI[0:3], GBL, TBST, TSIZ[0:2], TT[0:3], QACK, TA,TBEN, TEA, TS, EXT_QUAL, PMON_IN, SHD[0:1] Input hold times: A[0:35], AP[0:4] D[0:63], DP[0:7] AACK, ARTRY, BG, CKSTP_IN, DBG, DTI[0:3], GBL, TBST, TSIZ[0:2], TT[0:3], QACK, TA,TBEN, TEA, TS, EXT_QUAL, PMON_IN, SHD[0:1] Output valid times: A[0:35], AP[0:4] D[0:63], DP[0:7] AACK, ARTRY, BG, CKSTP_IN, DBG, DTI[0:3], GBL, TBST, TSIZ[0:2], TT[0:3], QACK, TA,TBEN, TEA, TS, EXT_QUAL, PMON_IN, SHD[0:1] Output hold times: A[0:35], AP[0:4] D[0:63], DP[0:7] AACK, ARTRY, BG, CKSTP_IN, DBG, DTI[0:3], GBL, TBST, TSIZ[0:2], TT[0:3], QACK, TA,TBEN, TEA, TS, EXT_QUAL, PMON_IN, SHD[0:1] SYSCLK to output enable SYSCLK to output high impedance (all except TS, ARTRY, SHD0, SHD1) SYSCLK to TS high impedance after precharge Maximum delay to ARTRY/SHD0/SHD1 precharge tMVRH tMXRH tAVKH tDVKH tIVKH 8 0 2.0 2.0 2.0 Max -- -- -- -- -- tSYSCLK ns ns 3, 4, 5, 6 3, 6 Unit Notes
ns tAXKH tDXKH tIXKH 0 0 0 -- -- --
ns tKHAV tKHDV tKHOV -- -- -- 2.5 2.5 2.5
ns tKHAX tKHDX tKHOX 0.5 0.5 0.5 -- -- --
tKHOE tKHOZ tKHTSPZ tKHARP
0.5 -- -- --
-- 3.5 1 1
ns ns tSYSCLK tSYSCLK 5, 7, 10 5, 8, 9, 10
MOTOROLA
MPC7457 Part Number Specification for the MPC74x7RXnnnnNx Series PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE
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General Parameters Table 1-9. Processor Bus AC Timing Specifications 1 (continued)
At recommended operating conditions. See Table 4.
All Speed Grades Parameter Symbol 2 Min SYSCLK to ARTRY/SHD0/SHD1 high impedance after precharge tKHARPZ -- Max 2 tSYSCLK 5, 8, 9, 10 Unit Notes
Notes: 1. All input specifications are measured from the midpoint of the signal in question to the midpoint of the rising edge of the input SYSCLK. All output specifications are measured from the midpoint of the rising edge of SYSCLK to the midpoint of the signal in question. All output timings assume a purely resistive 50- load (see Figure 4). Input and output timings are measured at the pin; time-of-flight delays must be added for trace lengths, vias, and connectors in the system. 2. The symbology used for timing specifications herein follows the pattern of t(signal)(state)(reference)(state) for inputs and t(reference)(state)(signal)(state) for outputs. For example, tIVKH symbolizes the time input signals (I) reach the valid state (V) relative to the SYSCLK reference (K) going to the high (H) state or input setup time. And tKHOV symbolizes the time from SYSCLK(K) going high (H) until outputs (O) are valid (V) or output valid time. Input hold time can be read as the time that the input signal (I) went invalid (X) with respect to the rising clock edge (KH) (note the position of the reference and its state for inputs) and output hold time can be read as the time from the rising edge (KH) until the output went invalid (OX). 3. The setup and hold time is with respect to the rising edge of HRESET (see Figure 5). 4. This specification is for configuration mode select only. 5. tSYSCLK is the period of the external clock (SYSCLK) in ns. The numbers given in the table must be multiplied by the period of SYSCLK to compute the actual time duration (in ns) of the parameter in question. 6. Mode select signals are: BVSEL, L3VSEL, PLL_CFG[0:4], BMODE[0:1]. 7. According to the bus protocol, TS is driven only by the currently active bus master. It is asserted low then precharged high before returning to high impedance as shown in Figure 6. The nominal precharge width for TS is 0.5 x tSYSCLK, that is, less than the minimum tSYSCLK period, to ensure that another master asserting TS on the following clock will not contend with the precharge. Output valid and output hold timing is tested for the signal asserted. Output valid time is tested for precharge.The high-impedance behavior is guaranteed by design. 8. According to the bus protocol, ARTRY can be driven by multiple bus masters through the clock period immediately following AACK. Bus contention is not an issue because any master asserting ARTRY will be driving it low. Any master asserting it low in the first clock following AACK will then go to high impedance for one clock before precharging it high during the second cycle after the assertion of AACK. The nominal precharge width for ARTRY is 1.0 tSYSCLK; that is, it should be high impedance as shown in Figure 6 before the first opportunity for another master to assert ARTRY. Output valid and output hold timing is tested for the signal asserted.The high-impedance behavior is guaranteed by design. 9. According to the MPX bus protocol, SHD0 and SHD1 can be driven by multiple bus masters beginning the cycle of TS. Timing is the same as ARTRY, that is, the signal is high impedance for a fraction of a cycle, then negated for up to an entire cycle (crossing a bus cycle boundary) before being three-stated again. The nominal precharge width for SHD0 and SHD1 is 1.0 tSYSCLK. The edges of the precharge vary depending on the programmed ratio of core to bus (PLL configurations). 10. Guaranteed by design and not tested.
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MPC7457 Part Number Specification for the MPC74x7RXnnnnNx Series PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE
MOTOROLA
General Parameters
1.5.2.3
L3 Clock AC Specifications
Table 10 provides the potential range of L3_CLK output AC timing specifications for the MPC7457 part numbers described herein.
Table 1-10. L3_CLK Output AC Timing Specifications
At recommended operating conditions. See Table 4.
All Speed Grades Parameter Symbol Min L3 clock frequency L3 clock cycle time L3 clock duty cycle L3 clock output-to-output skew (L1_CLK0 to L1_CLK1) L3 clock output-to-output skew (L1_CLK[0:1] to L1_ECHO_CLK[2:3]) L3 clock jitter fL3_CLK tL3_CLK tCHCL/tL3_CLK tL3CSKW1 tL3CSKW2 -- -- -- TBD TBD 50 TBD TBD TBD Max TBD TBD MHz ns % ps ps ps 2 3 4 5 1 Unit Notes
Notes: 1. The maximum L3 clock frequency will be system dependent. See Section 1.5.2.3, "L3 Clock AC Specifications," for an explanation that this maximum frequency is not functionally tested at speed by Motorola. 2. The nominal duty cycle of the L3 output clocks is 50% measured at midpoint voltage. 3. Maximum possible skew between L3_CLK0 and L3_CLK1. This parameter is critical to the address and control signals which are common to both SRAM chips in the L3. 4. Maximum possible skew between L3_CLK0 and L3_ECHO_CLK1 or between L3_CLK1 and L3_ECHO_CLK3 for PB2 or late write SRAM. This parameter is critical to the write data signals which are separately latched onto each SRAM part by these pairs of signals. 5. Guaranteed by design and not tested. The input jitter on SYSCLK affects L3 output clocks and the L3 address/data/ control signals equally and, therefore, is already comprehended in the AC timing and does not have to be considered in the L3 timing analysis. The clock-to-clock jitter shown here is uncertainty in the internal clock period caused by supply voltage noise or thermal effects. This must be accounted for, along with clock skew, in any L3 timing analysis.
MOTOROLA
MPC7457 Part Number Specification for the MPC74x7RXnnnnNx Series PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE
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General Parameters
1.5.2.4.1
L3 Bus AC Specifications for DDR MSUG2 SRAMs
Table 12 provides the L3 bus interface AC timing specifications for MSUG2 for the MPC7457 part numbers described herein.
Table 12. L3 Bus Interface AC Timing Specifications for MSUG2
At recommended operating conditions. See Table 4.
All Speed Grades Parameter Symbol Min L3_CLK rise and fall time Setup times: Data and parity Input hold times: Data and parity Valid times: Data and parity Valid times: All other outputs Output hold times: Data and parity Output hold times: All other outputs L3_CLK to high impedance: Data and parity L3_CLK to high impedance: All other outputs tL3CR, tL3CF tL3DVEH, tL3DVEL tL3DXEH, tL3DXEL tL3CHDV, tL3CLDV tL3CHOV tL3CHDX, tL3CLDX, tL3CHOX tL3CLDZ tL3CHOZ -- TBD TBD -- -- TBD TBD -- -- Max TBD -- -- TBD TBD -- -- TBD TBD ns ns ns ns ns ns ns ns ns 1 2, 3, 4 2, 4 5, 6, 7 5, 7 5, 6, 7 5, 7 Unit Notes
Notes: 1. Rise and fall times for the L3_CLK output are measured from 20% to 80% of GVDD. 2. For DDR, all input specifications are measured from the midpoint of the signal in question to the midpoint voltage of the rising or falling edge of the input L3_ECHO_CLKn (see Figure 10 in the MPC7457 RISC Microprocessor Hardware Specifications). Input timings are measured at the pins. 3. For DDR, the input data will typically follow the edge of L3_ECHO_CLKn as shown in Figure 10 in the MPC7457 RISC Microprocessor Hardware Specifications. For consistency with other input setup time specifications, this will be treated as negative input setup time. 4. tL3_ECHO_CLK/4 is one-fourth the period of L3_ECHO_CLKn. This parameter indicates that the MPC7457 can latch an input signal that is valid for only a short time before and a short time after the midpoint between the rising and falling (or falling and rising) edges of L3_ECHO_CLKn at any frequency. 5. All output specifications are measured from the midpoint voltage of the rising (or for DDR write data, also the falling) edge of L3_CLK to the midpoint of the signal in question. The output timings are measured at the pins. All output timings assume a purely resistive 50- load (see Figure 8 in the MPC7457 RISC Microprocessor Hardware Specifications). 6. For DDR, the output data will typically lead the edge of L3_CLKn as shown in Figure 10 in the MPC7457 RISC Microprocessor Hardware Specifications. For consistency with other output valid time specifications, this will be treated as negative output valid time. 7. tL3_CLK/4 is one-fourth the period of L3_CLKn. This parameter indicates that the specified output signal is actually launched by an internal clock delayed in phase by 90. Therefore, there is a frequency component to the output valid and output hold times such that the specified output signal will be valid for approximately one L3_CLK period starting three-fourths of a clock prior to the edge on which the SRAM will sample it and ending one-fourth of a clock period after the edge it will be sampled. 8. These configuration bits allow the AC timing of the L3 interface to be altered via software. They must be both set or both cleared; other configurations will increase tL3CSKW1, which may cause unreliable L3 operation.
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MPC7457 Part Number Specification for the MPC74x7RXnnnnNx Series PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE
MOTOROLA
General Parameters
1.5.2.4.2
L3 Bus AC Specifications for PB2 and Late Write SRAMs
Table 13 provides the L3 bus AC timing specifications for PB2 and Late Write SRAMs for the MPC7457 part numbers described herein.
Table 13. L3 Bus Interface AC Timing Specifications for PB2 and Late Write SRAMs
At recommended operating conditions. See Table 4.
All Speed Grades Parameter Symbol Min L3_CLK rise and fall time Setup times: Data and parity Input hold times: Data and parity Valid times: Data and parity Valid times: All other outputs Output hold times: Data and parity Output hold times: All other outputs L3_CLK to high impedance: Data and parity L3_CLK to high impedance: All other outputs tL3CR, tL3CF tL3DVEH tL3DXEH tL3CHDV tL3CHOV tL3CHDX tL3CHOX tL3CHDZ tL3CHOZ -- TBD -- -- -- TBD TBD -- -- Max TBD -- TBD TBD TBD -- -- TBD TBD ns ns ns ns ns ns ns ns ns 1, 5 2, 5 2, 5 3, 4, 5 4 3, 4, 5 4, 5 5 5 Unit Notes
Notes: 1. Rise and fall times for the L3_CLK output are measured from 20% to 80% of GVDD. 2. All input specifications are measured from the midpoint of the signal in question to the midpoint voltage of the rising edge of the input L3_ECHO_CLKn (see Figure 10 in the MPC7457 RISC Microprocessor Hardware Specifications). Input timings are measured at the pins. 3. All output specifications are measured from the midpoint voltage of the rising edge of L3_CLKn to the midpoint of the signal in question. The output timings are measured at the pins. All output timings assume a purely resistive 50- load (see Figure 10 in the MPC7457 RISC Microprocessor Hardware Specifications). 4. tL3_CLK/4 is one-fourth the period of L3_CLKn. This parameter indicates that the specified output signal is actually launched by an internal clock delayed in phase by 90. Therefore, there is a frequency component to the output valid and output hold times such that the specified output signal will be valid for approximately one L3_CLK period starting three-fourths of a clock prior to the edge on which the SRAM will sample it and ending one-fourth of a clock period after the edge it will be sampled. 5. Timing behavior and characterization are currently being evaluated. 6. These configuration bits allow the AC timing of the L3 interface to be altered via software. They must be both set or both cleared; other configurations will increase tL3CSKW1 and tL3CSKW2, which may cause unreliable L3 operation.
MOTOROLA
MPC7457 Part Number Specification for the MPC74x7RXnnnnNx Series PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE
9
Ordering Information
1.11 Ordering Information
1.11.1 Part Numbers Addressed by This Specification
Table 21 provides the ordering information for the MPC7457 parts described in this document.
Table 21. Part Marking Nomenclature
XPC
Product Code XPC 2
74x7
Part Identifier 7457 7447
RX
Package RX = CBGA
nnn
Processor Frequency 1 1000
x
Application Modifier N: 1.1 V 50 mV 0 to 105C
x
Revision Level B: 1.1; PVR = 8001 0201
Notes: 1. Processor core frequencies supported by parts addressed by this specification only. Parts addressed by other specifications may support other maximum core frequencies. 2. The X prefix in a Motorola part number designates a "Pilot Production Prototype" as defined by Motorola SOP 3-13. These are from a limited production volume of prototypes manufactured, tested, and Q.A. inspected on a qualified technology to simulate normal production. These parts have only preliminary reliability and characterization data. Before pilot production prototypes may be shipped, written authorization from the customer must be on file in the applicable sales office acknowledging the qualification status and the fact that product changes may still occur while shipping pilot production prototypes.
1.11.3 Part Marking
Parts are marked as the example shown in Figure 29.
XPC7447 RX10000NB MMMMMM ATWLYYWWA
XPC7457 RX1000NB MMMMMM ATWLYYWWA
7447 BGA
7457
BGA Notes: MMMMMM is the 6-digit mask number. ATWLYYWWA is the traceability code. CCCCC is the country of assembly. This space is left blank if parts are assembled in the United States.
Figure 29. Motorola Part Marking for BGA Devices
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MPC7457 Part Number Specification for the MPC74x7RXnnnnNx Series PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE
MOTOROLA
Document Revision History
Document Revision History
Table B provides a revision history for this part number specification.
Table B. Document Revision History
Rev. No. 0 Initial release. Substantive Change(s)
MOTOROLA
MPC7457 Part Number Specification for the MPC74x7RXnnnnNx Series PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE
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